The present invention relates to address scheduling of a flash memory device and, more particularly, to a method of operating a flash memory device including Multi-Level Cells (MLCs) capable of storing a plurality of data bits.
Flash memory is generally classified into NAND type flash memory and NOR type flash memory. NOR type flash memory has a structure in which memory cells are independently connected to bit lines and word lines and, therefore, exhibits a good random access time characteristic. NAND type flash memory requires only one contact per cell string since a plurality of memory cells are connected and therefore exhibits excellent integration degree characteristics. Accordingly, the NAND structure has generally been used for highly-integrated flash memory.
In recent years, in order to further increase the integration degree of the flash memory, a multi-bit cell has been developed that can store a plurality of data in one memory cell. This type of memory cell is generally referred to as a Multi level Cell (MLC). A memory cell that stores a single bit of data is referred to as a Single Level Cell (SLC).
In general, when N bits can be stored, an MLC has N threshold voltage distributions. An MLC includes N pages to perform a program on each bit with respect to one word line. In the MLC, a program or read operation is performed on the N pages. In other words, in a flash memory device including an MLC capable of storing N-bit data, a program or read operation is performed by dividing the threshold voltage (Vth) based on a page in order to represent N bits.
In general, in N-bit flash memory devices, to implement grey code and reduce interference, the program or read operation is performed by allocating a page, having a wide cell threshold voltage variation, to a lower position.
When storing N-bit data in a cell of MLC flash memory, interference in which the threshold voltage of adjacent cells is changed due to coupling between the adjacent cells is proportional to a variation in the cell threshold voltage.
Accordingly, to program data into a MLC flash memory device and read data programmed into a MLC flash memory device, a variety of methods for minimizing interference are employed.